Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions (English)
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In:
ESSDERC, European Solid-State Device Research Conference, 35
;
445-448
;
2005
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ISBN:
- Conference paper / Print
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Title:Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions
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Contributors:Dixit, A. ( author ) / Anil, K.G. ( author ) / Rooyackers, R. ( author ) / Kaiser, M. ( author ) / Weemaes, R. ( author ) / Ferain, I. ( author ) / De Keersgieter, A. ( author ) / Collaert, N. ( author ) / Surdeanu, R. ( author ) / Goodwin, M. ( author )
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Published in:
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Publisher:
- New search for: IEEE Operations Center
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Place of publication:Piscataway
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Publication date:2005
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Size:4 Seiten, 11 Quellen
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ISBN:
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DOI:
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Type of media:Conference paper
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Type of material:Print
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Language:English
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Keywords:
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
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Proceedings of ESSDERC 2005 35th European Solid-State Device Research Conference| 2005
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Dos epaisseur 50mm a verifier avec l'imprimeur suivant le nombre de pages| 2005
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Copyright| 2005
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Technical sponsorship| 2005
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Foreword| 2005
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Conference organization| 2005
- 1
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Keynote papers| 2005
- 3
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"Silicon forever! Really?"Stormer, H.L. et al. | 2005
- 7
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Future devices for information processingCavin, R.K. / Zhirnov, V.V. et al. | 2005
- 13
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Terahertz technology: devices and applicationsShur, M. et al. | 2005
- 23
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Silicon nano-photonics: where the photons meet the electronsYablonovitch, E. et al. | 2005
- 27
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Towards a molecule - computer? Resources and technologies to compute within a single moleculeJoachim, C. et al. | 2005
- 29
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Engineering wafers for the nanotechnology eraMazure, C. / Auberton-Herve, A.-J. et al. | 2005
- 39
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Digital control of RF power amplifiers for next-generation wireless communicationsLarson, L. / Asbeck, P. / Kimball, D. et al. | 2005
- 45
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Analog/RF circuit design techniques for nanometerscale IC technologiesNauta, B. / Annema, A.-J. et al. | 2005
- 55
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Nanoelectronics: nanotubes, nanowires, molecules, and novel conceptsWong, P.H.-S. et al. | 2005
- 63
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Pushing CMOS beyond the roadmapRisch, L. et al. | 2005
- 69
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Smart cards insideGammel, B.M. / Ruping, S.J. et al. | 2005
- 75
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Session papers| 2005
- 77
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3-D thermal modeling of finFETJoshi, R.V. / Pascual-Gutierrez, J.A. / Chuang, C.T. et al. | 2005
- 81
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Immunity to substrate effect in advanced /spl Omega/FET devicesRitzenthaler, R. / Faynot, O. / Jahan, C. / Kuriyama, A. / Brevard, L. / Deleonibus, S. / Cristoloveanu, S. et al. | 2005
- 85
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Specific features of the capacitance and mobility behaviors in FinFET structuresRudenko, T. / Kilchytska, V. / Collaert, N. / De Gendt, S. / Rooyackers, R. / Jurczak, M. / Flandre, D. et al. | 2005
- 89
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Evidence for reduction of noise and radiation effects in G/sup 4/-FET depletion-all-around operationAkarvardar, K. / Cristoloveanu, S. / Dufrene, B. / Gentil, P. / Schrimpf, R.D. / Blalock, B.J. / Chroboczek, J.A. / Mojarradi, M. et al. | 2005
- 93
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Tunneling and intersubband coupling in ultra-thin body double-gate MOSFETsSverdlov, V. / Gehring, A. / Kosina, H. / Selberherr, S. et al. | 2005
- 97
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Germanium/HfO2/TiN gate stacks for advanced nodes: Influence of surface preparation on MOS capacitor characteristicsRoyer, C. le / Garros, X. / Tabone, C. / Clavelier, L. / Morand, Y. / Hartmann, J.M. / Campidelli, Y. / Kermarrec, O. / Loup, V. / Martinez, E. et al. | 2005
- 97
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Germanium/HfO/sub 2//TiN gate stacks for advanced nodes: influence of surface preparation on MOS capacitor characteristicsLe Royer, C. / Garros, X. / Tabone, C. / Clavelier, L. / Morand, Y. / Hartmann, J.-M. / Campidelli, Y. / Kermarrec, O. / Loup, V. / Martinez, E. et al. | 2005
- 101
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The effect of metal thickness, overlayer and high-k surface treatment on the effective work function of metal electrodeChoi, K. / Wen, H.-C. / Alshareef, H. / Harris, R. / Lysaght, P. / Luan, H. / Majhi, P. / Lee, B.H. et al. | 2005
- 105
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Mixed-signal and noise properties of nMOSFETs with HfSiON/TaN Gate StacksRittersma, Z.M. / Simoen, E. / Srinivasan, P. / Vertregt, M. / Claeys, C. et al. | 2005
- 109
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Work function control of metal gates by interdiffused Ni-Ta with high thermal stabilityMatsukawa, T. / Liu, Y.X. / Masahara, M. / Endo, K. / Ishii, K. / Yamauchi, H. / Sugimata, E. / Takashima, H. / Kanemaru, S. / Suzuki, E. et al. | 2005
- 113
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Plasma doping for S/D extensions: device integration, gate oxide reliability and dynamic behaviorDumont, B. / Pouydebasque, A. / Lallement, F. / Lenoble, D. / Ribes, G. / Roux, J.-M. / Vanbergue, S. / Skotnicki, T. et al. | 2005
- 117
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High-performance varactor diodes integrated in a silicon-on-glass technologyBuisman, K. / Nanver, L.K. / Scholtes, T.L.M. / Schellevis, H. / de Vreede, L.C.N. et al. | 2005
- 121
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Three-dimensional 35 nF/mm/sup 2/ MIM capacitors integrated in BiCMOS technologyBajolet, A. / Giraudin, J.C. / Rossato, C. / Pinzelli, L. / Bruyere, S. / Cremer, S. / Jagueneau, T. / Delpech, P. / Montes, L. / Ghibaudo, G. et al. | 2005
- 125
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- 129
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- 133
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Investigation of fully- and partially-depleted self-aligned SiGeC HBTs on thin film SOIAvenier, G. / Chevalier, P. / Vandelle, B. / Lenoble, D. / Saguin, F. / Fregonese, S. / Zimmer, T. / Chantre, A. et al. | 2005
- 137
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Quantum short-channel compact modeling of drain-current in double-gate MOSFETMunteanu, D. / Autran, J.-L. / Loussier, X. / Harrison, S. / Cerutti, R. / Skotnickit, T. et al. | 2005
- 141
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Compact modeling of anomalous high frequency behavior of MOSFET's small-signal NQS parameters in presence of velocity saturationRoy, A.S. / Sallese, J.M. / Enz, C.C. et al. | 2005
- 145
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Compact modeling of electrical, thermal and optical LED behaviorBaureis, P. et al. | 2005
- 149
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A closed-form charge-based expression for drain current in symmetric and asymmetric double gate MOSFETRoy, A.S. / Sallese, J.-M. / Enz, C.C. et al. | 2005
- 153
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Base-collector junction charge investigation of Si/SiGe HBT on thin film SOIFregonese, S. / Avenier, G. / Maneux, C. / Chantre, A. / Zimmer, T. et al. | 2005
- 157
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Nanotechnology: potential challenger to silicon CMOS?Yu, B. / Meyyappan, M. et al. | 2005
- 161
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Quantum-mechanical analysis of the electrostatics in silicon-nanowire and carbon-nanotube FETsGnani, E. / Marchi, A. / Reggiani, S. / Rudan, M. / Baccarani, G. et al. | 2005
- 165
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Trade-off between electron velocity and density of states in ballistic nano-MOSFETsDe Michielis, M. / Esseni, D. / Driussi, F. et al. | 2005
- 169
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Monte Carlo simulations of sub-100 nm InGaAs MOSFETs for digital applicationsKalna, K. / Yang, L. / Asenov, A. et al. | 2005
- 173
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The 65nm tunneling field effect transistor (TFET) 0.68/spl mu/m/sup 2/ 6T memory cell and multi-V/sub th/ deviceNirschl, T. / Henzler, St. / Fischer, J. / Bargagli-Stoffi, A. / Fulde, M. / Sterkel, M. / Teichmann, P. / Schaper, U. / Einfeld, J. / Linnenbank, C. et al. | 2005
- 173
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The 65 nm tunneling field effect transistor (TFET) 0.68 micron2 6T memory cell and multi-Vth deviceNirschl, T. / Henzler, S. / Fischer, J. / Bargagli-Stoffi, A. / Fulde, M. / Sterkel, M. / Teichmann, P. / Schaper, U. / Einfeld, J. / Linnenbank, C. et al. | 2005
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High-density low-power-operating DRAM device adopting 6F2 cell scheme with novel S-RCAT structure on 80 nm feature size and beyondOh, H.J. / Kim, J.Y. / Kim, J.H. / Park, S.G. / Kim, D.H. / Kim, S.E. / Woo, D.S. / Lee, Y.S. / Ha, G.W. / Park, J.M. et al. | 2005
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High-density low-power-operating DRAM device adopting 6F/sup 2/ cell scheme with novel S-RCAT structure on 80nm feature size and beyondOh, H.J. / Kim, J.Y. / Kim, J.H. / Park, S.G. / Kim, D.H. / Kim, S.E. / Woo, D.S. / Lee, Y.S. / Ha, G.W. / Park, J.M. et al. | 2005
- 181
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Advanced memory concepts for DRAM and nonvolatile memoriesHoriguchi, F. et al. | 2005
- 185
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Data retention analysis on individual cells of 256Mb DRAM i n 110nm technologyWeber, A. / Birner, A. / Krautschneider, W. et al. | 2005
- 189
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Enhancement of data retention time in DRAM using step gated asymmetric (STAR) cell transistorsJang, M.W. / Seo, M.S. / Kim, Y.T. / Cha, S.Y. / Kim, Y.B. / Kim, S.C. / Rhee, J.H. / Cheong, J.T. / Jung, T.W. / Pyi, S.H. et al. | 2005
- 193
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Analysis of the NAND-type DRAM-on-SGT for high-density and low-voltage memoryNakamura, H. / Pesic, I. / Sakuraba, H. / Masuoka, F. et al. | 2005
- 197
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Polarity dependence of bias temperature instabilities in Hf/sub x/Si/sub 1-x/ON/TaN gate stacksAoulaiche, M. / Houssa, M. / Degraeve, R. / Groeseneken, G. / De Gendt, S. / Heyns, M.M. et al. | 2005
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Polarity dependence of bias temperature instabilities in Hf(x)Si(1-x)ON/TaN gate stacksAoulaiche, M. / Houssa, M. / Degraeve, R. / Groeseneken, G. / Gendt, S. de / Heyns, M.M. et al. | 2005
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The role of nitrogen incorporation in Hf-based high-k dielectrics: reduction in electron charge trapsUmezawa, N. / Shiraishi, K. / Torii, K. / Boero, M. / Chikyow, T. / Watanabe, H. / Yamabe, K. / Ohno, T. / Yamada, K. / Nara, Y. et al. | 2005
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Effects of plasma nitridation on the electrical properties of nitrided oxide gate dielectric for DRAM applicationJin-Hwa Heo, / Dong-Chan Kim, / Bon-Young Koo, / Ji-Hyun Kim, / Chul-Sung Kim, / Young-Jin Noh, / Sung-Kweon Baek, / Yu-Gyun Shin, / U-In Chung, / Joo-Tae Moon, et al. | 2005
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Analytical model for nanowire and nanotube transistors covering both dissipative and ballistic transportMugnaini, G. / Iannaccone, G. et al. | 2005
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Impact of point defect location in nanowire silicon MOSFETsBescond, M. / Cavassilas, N. / Nehari, K. / Autran, J.-L. / Lannoo, M. / Asenov, A. et al. | 2005
- 225
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Detection of individual traps in silicon nanowire transistorsHofheinz, M. / Jehl, X. / Sanquer, M. / Molas, G. / Vinet, M. / Deleonibus, S. et al. | 2005
- 229
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Influence of band-structure on electron ballistic transport in silicon nanowire MOSFET's: an atomistic studyNehari, K. / Cavassilas, N. / Autran, J.L. / Bescond, M. / Munteanu, D. / Lannoo, M. et al. | 2005
- 233
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Efficient crosstalk reduction using very low resistivity SOI substrateAnkarcrona, J. / Vestling, L. / Eklund, K.-H. / Olsson, J. et al. | 2005
- 237
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SOA improvement of p-channel high-voltage SOI devicesSchwantes, S. / Graf, M. / Dudek, V. et al. | 2005
- 241
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SOI CMOS technology for RF/MMIC applications - yes or no?Ru Huang, / Huailin Liao, / Guoyan Zhang, et al. | 2005
- 245
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Temperature dependence of avalanche multiplication in submicron silicon devicesMassey, D.J. / David, J.P.R. / Rees, G.J. et al. | 2005
- 249
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Digital logic using magnetic nanostructuresCowbum, R.P. et al. | 2005
- 253
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Modeling of polymer Schottky diodes for real device applicationsRaja, M. / Sedghi, N. / Badriya, S. / Higgins, S.J. / Lloyd, G.C.R. / Eccleston, W. et al. | 2005
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High-speed InP-based resonant tunneling diode on silicon substrateProst, W. / Khorenko, V. / Mofor, A.C. / Bakin, A. / Khorenko, E. / Ehrich, S. / Wehmann, H.-H. / Schlachetzki, A. / Tegude, F.-J. et al. | 2005
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High-speed InP-based resonant tunnelling diode on silicon substrateProst, W. / Khorenko, V. / Mofor, A.C. / Bakin, A. / Khorenko, E. / Ehrich, S. / Wehmann, H.H. / Schlachetzki, A. / Tegude, F.J. et al. | 2005
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/spl mu/trench phase-change memory cell engineering and optimizationPirovano, A. / Pellizzer, F. / Redaelli, A. / Tortorelli, I. / Varesi, E. / Ottogalli, F. / Tosi, M. / Besana, P. / Cecchini, R. / Piva, R. et al. | 2005
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Modeling MOSFET and circuit degradation through SPICECester, A. / Gerardin, S. / Paccagnella, A. / Ghidini, G. et al. | 2005
- 407
-
Charge trapping effects and interface state generation in a 40 V lateral resurf pDMOS transistorMoens, P. / Van den bosch, G. / Wojciechowski, D. / Bauwens, F. / De Vleeschouwer, H. / De Pestel, F. et al. | 2005
- 411
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Predictive device simulation for ESD protection structures validated with transient interferometric thermal-mapping experimentsReggiani, S. / Gnani, E. / Rudan, M. / Baccarani, G. / Bychikhin, S. / Kuzmik, J. / Pogany, D. / Gornik, E. / Denison, M. / Jensen, N. et al. | 2005
- 415
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Interaction of middle-of-line (MOL) temperature and mechanical stress on 90nm hi-speed device performance and reliabilityLim, K.Y. / Chan, V. / Rengarajan, R. / Lee, H.K. / Rovedo, N. / Lim, E.H. / Yang, S. / Jamin, F. / Nguyen, P. / Lin, W. et al. | 2005
- 419
-
CMOS integration of solid phase epitaxy for sub-50nm devicesPouydebasque, A. / Dumont, B. / El-Farhane, R. / Halimaouit, A. / Laviron, C. / Lenoblet, D. / Rossato, C. / Casanova, N. / Carron, V. / Pokrant, S. et al. | 2005
- 423
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65nm LP/GP mix low cost platform for multi-media wireless and consumer applicationsTavel, B. / Duriez, B. / Gwoziecki, R. / Basso, M.T. / Julien, C. / Ortolland, C. / Laplanche, Y. / Fox, R. / Saboure, E. / Detcheverry, C. et al. | 2005
- 427
-
Silicidation induced strain phenomena in totally silicided (TOSI) gate transistorsMondot, A. / Muller, M. / Aime, D. / Froment, B. / Cacho, F. / Talbot, A. / Leverd, F. / Rivoire, M. / Morand, Y. / Descombes, S. et al. | 2005
- 431
-
Demonstration of high performance transistors with PVD metal gateHarris, H.R. / Wen, H.C. / Choi, K. / Alshareef, H. / Luan, H. / Senzaki, Y. / Young, C.D. / Song, S.C. / Zhang, Z. / Bersuker, G. et al. | 2005
- 435
-
Insight on physics of Hf-based dielectrics reliabilityRibes, G. / Denais, M. / Bruyere, S. / Roy, D. / Monsieur, F. / Huard, V. / Parthasarthy, C. / Muller, M. / Skotnicki, T. / Ghibaudo, G. et al. | 2005
- 439
-
Intrinsic limitations for CMOS with high-k gate dielectrics: electrically-active grain boundary and oxygen atom defect statesLucovsky, G. / Luning, J. et al. | 2005
- 445
-
Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regionsDixit, A. / Anil, K.G. / Rooyackers, R. / Kaiser, M. / Weemaes, R. / Ferain, I. / De Keersgieter, A. / Collaert, N. / Surdeanu, R. / Goodwin, M. et al. | 2005
- 449
-
Scalability of strained nitride capping layers for future CMOS generationsEneman, G. / Jurczak, M. / Verheyen, P. / Hoffmann, T. / De Keersgieter, A. / De Meyer, K. et al. | 2005
- 453
-
CMP-less integration of 40nm-gate totally silicided (TOSI) bulk transistors using selective S/D Si epitaxy and ultra-low gatesMuller, M. / Mondot, A. / Aime, D. / Froment, B. / Talbot, A. / Roux, J.-M. / Ribes, G. / Morand, Y. / Descombes, S. / Gouraud, P. et al. | 2005
- 457
-
Schottky barrier height modulation using dopant segregation in Schottky-barrier SOI-MOSFETsZhang, M. / Knoch, J. / Zhao, Q.T. / Lenk, St. / Breuer, U. / Mantl, S. et al. | 2005
- 461
-
Base-contact proximity effects in bipolar transistors with nitride-spacer technologyvan Zeijl, H. / Nanver, L.K. et al. | 2005
- 465
-
Characterization of dynamic SOA of power MOSFETs limited by electrothermal breakdownVan den bosch, G. / Wojciechowski, D. / Elattari, B. / Moens, P. / Groeseneken, G. et al. | 2005
- 469
-
LDMOS modeling for analog and RF circuit designCanepari, A. / Bertrand, G. / Giry, A. / Minondo, M. / Blanchet, F. / Jaouen, H. / Reynard, B. / Jourdan, N. / Chante, J.-P. et al. | 2005
- 473
-
Monolithic bidirectional switch (MBS) - a novel MOS-based power deviceBaus, M. / Ali, M.Z. / Winkler, O. / Spangenberg, B. / Lemme, M.C. / Kurz, H. et al. | 2005
- 477
-
Low switching losses devices architectures for power management applications integrated in a low cost 0.13 mu m CMOS technologyGrelu, C. / Baboux, N. / Bianchi, R.A. / Plossu, C. et al. | 2005
- 477
-
Low switching losses devices architectures for power management applications integrated in a low cost 0.13/spl mu/m CMOS technologyGrelu, C. / Baboux, N. / Bianchi, R.A. / Plossu, C. et al. | 2005
- 481
-
The impact of channel engineering on the performance and reliability of LDMOS transistorsMohapatra, N.R. / Ehwald, K.E. / Barth, R. / Rucker, H. / Bolze, D. / Schley, P. / Schmidt, D. / Wulf, H.E. et al. | 2005
- 485
-
Integration of substrate-isolated high voltage devices in junction isolated technologiesPendharkar, S. et al. | 2005
- 489
-
A new method to calculate leakage current and its applications for sub-45nm MOSFETsLujan, G.S. / Magnus, W. / Soree, B. / Pourghaderi, M.A. / Veloso, A. / van Da, M.J.H. / Lauwers, A. / Kubicek, S. / De Gendt, S. / Heyns, M. et al. | 2005
- 493
-
Finite element simulation of thermomechanical stress evolution in Cu/low-k interconnects during manufacturing and subsequent thermal cyclingCherault, N. / Besson, J. / Goldberg, C. / Casanova, N. / Berger, M.-H. et al. | 2005
- 497
-
Simulation and characterization of high-frequency performances of advanced MIM capacitorsPiquet, J. / Cueto, O. / Charlet, F. / Thomas, M. / Bermond, C. / Farcy, A. / Torres, J. / Flechet, B. et al. | 2005
- 501
-
Wavelet-based adaptive mesh generation for device simulationDe Marchi, L. / Franze, F. / Baravelli, E. / Speciale, N. et al. | 2005
- 505
-
AC-SONOS: a single-poly, assist-charge induced source-side-injection SONOS low power nonvolatile memoryMing-Hsiu Lee, / Jau-Yi Wu, / Ming-Chang Kuo, / Tzu-Hsuan Hsu, / Hsiang-Lan Lung, / Tiao-Yuan Huang, / Rich Liu, / Chih-Yuan Lu, et al. | 2005
- 509
-
Experimental and theoretical study of layered tunnel barriers for nonvolatile memoriesBuckley, J. / De Salvo, B. / Molas, G. / Gely, M. / Deleonibus, S. et al. | 2005
- 513
-
Advanced ring type contact technology for high density phase change memorySong, Y.J. / Park, J.H. / Lee, S.Y. / Jae-Hyun Park, / Hwang, Y.N. / Lee, S.H. / Ryoo, K.C. / Ahn, S.J. / Jeong, C.W. / Shin, J.M. et al. | 2005
- 517
-
Improvement of the current-voltage characteristics of a tunneling dielectric by barrier engineering by adopting an atomic-layer-deposited SiN layer for flash memory applicationsSug Hun Hong, / Jae Hyuck Jang, / Tae Joo Park, / Doo Seok Jeong, / Miyoung Kim, / Cheol Seong Hwang, et al. | 2005
- 521
-
Extraction of physical parameters of strained silicon MOSFETs from C-V measurementChandrasekaran, K. / Xing Zhou, / Siau Ben Chiah, / Wangzuo Shangguan, / Guan Huei See, / Bera, L.K. / Balasubramanian, N. / Rustagi, S.C. et al. | 2005
- 525
-
Low temperature characterization of effective mobility in uniaxially and biaxially strained N-MOSFETsLime, F. / Andrieu, F. / Derix, J. / Ghibaudo, G. / Boeuf, F. / Skotnicki, T. et al. | 2005
- 529
-
Impact of strain and strain-relaxation on the low-frequency noise of SRB silicon n-MOSFETsSimoen, E. / Eneman, G. / Claeys, C. / Verheyen, P. / Delhougne, R. / Loo, R. / De Meyer, K. et al. | 2005
- 533
-
STI-induced damage and hot-carrier reliability in the narrow width short channel NMOSFET fabricated using global strained-Si technologyPhua, W.H.T. / Ang, D.S. / Ling, C.H. / Chui, K.J. et al. | 2005
- 537
-
Three-dimensional atomistic simulation of carbon nanotube FETs with realistic geometryFiori, G. / Iannaccone, G. / Lundstrom, M. / Klimeck, G. et al. | 2005
- 541
-
Improving DC and AC characteristics of ohmic contact carbon nanotube field effect transistorsPourfath, M. / Kosina, H. / Cheong, B.H. / Park, W.J. / Selberherr, S. et al. | 2005
- 545
-
Nanoscale capacitors based on metal-insulator-carbon nanotube-metal (MICNM) structuresJang, J.E. / Cha, S.N. / Choi, Y. / Kang, D.J. / Haskot, D.G. / Amaratunga, G.A.J. et al. | 2005
- 549
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65nm high performance SRAM technology with 25F2 0.16/spl mu/m/sup 2/ S/sup 3/ (stacked single-crystal Si) SRAM cell, and stacked peripheral SSTFT for ultra high density and high speed applicationsHoon Lim, / Soon-Moon Jung, / Youngseop Rah, / Taehong Ha, / Hanbyung Park, / Chulsoon Chang, / Wonsuk Cho, / Jaikyun Park, / Byoungkeun Son, / Jaehun Jeong, et al. | 2005
- 549
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65nm high performance SRAM technology with 25F2, 0.16um2S3 (Stacked Single-Crystal Si) SRAM cell, and stacked peripheral SSTFT for ultra high density and high speed applicationsLim, Hoon / Jung, Soon-Moon / Rah, Youngseop / Ha, Taehong / Park, Hanbyung / Chang, Chulsoon / Cho, Wonsuk / Park, Jaikyun / Son, Byoungkeun / Jeong, Jaehun et al. | 2005
- 553
-
UTB SOI SRAM cell stability under the influence of intrinsic parameter fluctuationSamsudin, K. / Cheng, B. / Brown, A.R. / Roy, S. / Asenov, A. et al. | 2005
- 557
-
A SrRuO3/IrO2 top electrode FeRAM with Cu BEOL process for embedded memory of 130 nm generation and beyondKumura, Y. / Ozaki, T. / Hidaka, O. / Shimojo, Y. / Shuto, S. / Yamada, Y. / Tomioka, K. / Yamakawa, K. / Yamazaki, S. / Takashima, D. et al. | 2005
- 557
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A SrRuO/sub 3//IrO/sub 2/ top electrode FeRAM with Cu BEOL process for embedded memory of 130nm generation and beyondKumura, Y. / Ozaki, T. / Kanaya, H. / Hidaka, O. / Shimojo, Y. / Shuto, S. / Yamada, Y. / Tomioka, K. / Yamakawa, K. / Yamazaki, S. et al. | 2005
- 561
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Influence of ballistic and pocket effects on electron mobility in Si MOSFETsLusakowski, J. / Knap, W. / Meziani, Y. / Cesso, J.P. / El Fatimy, A. / Tauk, R. / Dyakonova, N. / Ghibaudo, G. / Boeuf, F. / Skotnicki, T. et al. | 2005
- 565
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Experimental validation of a new analytical model for the position-dependent Hall voltage in semiconductor devicesRudan, M. / Reggiani, S. / Gnani, E. / Baccarani, G. / Corvasce, C. / Barlini, D. / Ciappa, M. / Fichtner, W. / Denison, M. / Jensen, N. et al. | 2005
- 569
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Magnetoresistance technique for mobility extraction in short channel FDSOI transistorsChaisantikulwat, W. / Mouis, M. / Ghibaudo, G. / Gallon, C. / Fenouillet-Beranger, C. / Maude, D.K. / Skotnicki, T. / Cristoloveanu, S. et al. | 2005
- 574
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Schedule| 2005
- 575
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Welcome| 2005
- 576
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Table of contents ESSDERC| 2005
- 577
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Conference organisation| 2005
- 578
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Committees| 2005
- 581
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General information| 2005
- 583
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Conference site| 2005
- 585
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Map conference facilities| 2005
- 587
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Conference registration| 2005
- 589
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Conference Information| 2005
- 590
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Social programme| 2005
- 591
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Accompanying persons programme| 2005
- 592
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ESSDERC-ESSCIRC Joint plenary talks| 2005
- 593
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ESSDERC-Invited plenary talks| 2005
- 594
-
ESSDERC-invited| 2005
- 597
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Short courses| 2005
- 626
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Table of contents| 2005
- 637
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ESSCIRC-invited plenary talks| 2005
- 672
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Notes| 2005
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Proceedings of ESSDERC 2005. 35th European Solid-State Device Research Conference (IEEE Cat. No. 05EX1087)| 2005