Exploiting bit level concurrency in real-time geometric feature extractions (English)
- New search for: Liu, W.
- New search for: Yeh, T.F.
- New search for: Batchelor, W.E.
- New search for: Cavin, R.
- New search for: Liu, W.
- New search for: Yeh, T.F.
- New search for: Batchelor, W.E.
- New search for: Cavin, R.
In:
15th Annual International Symposium on Computer Architecture. Conference Proceedings
;
167-174
;
1988
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ISBN:
- Conference paper / Print
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Title:Exploiting bit level concurrency in real-time geometric feature extractions
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Additional title:Die Ausnutzung der Bit-Ebenenverzahnung bei der geometrischen Merkmalextraktion in Echtzeit
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Contributors:
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Published in:
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Publisher:
- New search for: IEEE Comput. Soc. Press
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Place of publication:Washington
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Publication date:1988
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Size:8 Seiten, 28 Quellen
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ISBN:
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DOI:
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Type of media:Conference paper
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Type of material:Print
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Language:English
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Keywords:
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 0_1
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15th Annual International Symposium on Computer Architecture. Conference Proceedings (Cat. No.88CH2545-2)| 1988
- 3
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Critical issues in mapping neural networks on message-passing multicomputersGhosh, J. / Hwang, K. et al. | 1988
- 12
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Multinomial conjunctoid statistical learning machinesTakefuji, Y. / Jannarone, R. / Cho, Y.B. / Chen, T. et al. | 1988
- 30
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The reconfigurable arithmetic processorFiske, S. / Dally, W.J. et al. | 1988
- 56
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Analysis of memory referencing behavior for design of local memoriesMcNiven, G.D. / Davidson, E.S. et al. | 1988
- 64
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Performance evaluation of on-chip register and cache organizationsEickemeyer, R.J. / Patel, J.H. et al. | 1988
- 73
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On the inclusion properties for multi-level cache hierarchiesBaer, J.L. / Wang, W.H. et al. | 1988
- 81
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A simulation study of two-level cachesShort, R.T. / Levy, H.M. et al. | 1988
- 116
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A partial-multiple-bus computer structure with improved cost-effectivenessJiang, H. / Smith, K.C. et al. | 1988
- 141
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Resource requirements of dataflow programsCuller, D.E. / Arvind et al. | 1988
- 160
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A kernel-independent, pipelined architecture for real-time 2-D convolutionShukla, S.B. / Agrawal, D.P. et al. | 1988
- 167
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Exploiting bit level concurrency in real-time geometric feature extractionsLiu, W. / Yeh, T.F. / Batchelor, W.E. / Cavin, R. et al. | 1988
- 176
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Measuring VAX 8800 performance with a histogram hardware monitorClark, D.W. / Bannon, P.J. / Keller, J.B. et al. | 1988
- 186
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Multiprocessor cache analysis using ATUMSites, R.L. / Agarwal, A. et al. | 1988
- 204
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Design of a concurrent computer for solving systems of linear equationsJainandunsing, K. / Deprettere, E.F. et al. | 1988
- 212
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The White Dwarf: a high-performance application-specific processorWolfe, A. / Breternitz, M. jun. / Stephens, C. / Ting, A.L. / Kirk, D.B. / Bianchini, R.P. jun. / Shen, J.P. et al. | 1988
- 240
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The architecture of a Linda coprocessorKrishnaswamy, V. / Ahuja, S. / Carriero, N. / Gelernter, D. et al. | 1988
- 261
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Cache performance of vector processorsSo, K. / Zecca, V. et al. | 1988
- 280
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An evaluation of directory schemes for cache coherenceAgarwal, A. / Simoni, R. / Hennessy, J. / Horowitz, M. et al. | 1988
- 290
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Performance tradeoffs in cache designPrzybylski, S. / Horowitz, M. / Hennessy, J. et al. | 1988
- 299
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A cache coherence scheme with fast selective invalidationCheong, H. / Veidenbaum, A.V. et al. | 1988
- 318
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Destination tag routing techniques based on a state model for the IADM networkRau, D. / Fortes, J.A.B. / Siegel, H.J. et al. | 1988
- 373
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A characterization of sharing in parallel programs and its application to coherency protocol evaluationEggers, S.J. / Katz, R.H. et al. | 1988
- 401
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Design and performance of special purpose hardware for Time WarpFujimoto, R.M. / Tsai, J.J. / Gopalakrishnan, G. et al. | 1988
- 410
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The VMP multiprocessor: initial experience, refinements and performance evaluationCheriton, D.R. / Gupta, A. / Boyle, P.D. / Goosen, H.A. et al. | 1988
- 452
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Parallel architecture for OPS5Butler, P.L. / Allen, J.D. jun. / Bouldin, D.W. et al. | 1988