SIMP (single instruction stream/multiple instruction pipelining): a novel high-speed single processor architecture (English)
- New search for: Murakami, K.
- New search for: Irie, N.
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- New search for: Tomita, S.
- New search for: Murakami, K.
- New search for: Irie, N.
- New search for: Kuga, M.
- New search for: Tomita, S.
In:
16th Annual International Symposium on Computer Architecture
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78-85
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1989
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ISBN:
- Conference paper / Print
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Title:SIMP (single instruction stream/multiple instruction pipelining): a novel high-speed single processor architecture
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Additional title:SIMP, eine neuartige Architektur fuer Hochgeschwindigkeits-Monoprozessoren
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Contributors:
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Published in:
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Publisher:
- New search for: IEEE Comput. Soc. Press
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Place of publication:Washington
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Publication date:1989
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Size:8 Seiten, 21 Quellen
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ISBN:
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Type of media:Conference paper
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Type of material:Print
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Language:English
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Keywords:
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 2
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Evaluating the performance of four snooping cache coherency protocolsEggers, S.J. / Katz, R.H. et al. | 1989
- 16
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Multi-level shared caching techniques for scalability in VMP-MCCheriton, D.R. / Goosen, H.A. / Boyle, P.D. et al. | 1989
- 25
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Design and performance of a coherent cache for parallel logic programming architecturesGoto, A. / Matsumoto, A. / Tick, E. et al. | 1989
- 36
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The epsilon psilon dataflow processorGrafe, V.G. / Davidson, G.S. / Hoch, J.E. / Holmes, V.P. et al. | 1989
- 46
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An architecture of a dataflow single chip processorSakai, S. / Yamaguchi, Y. / Hiraki, K. / Kodama, Y. / Yuba, T. et al. | 1989
- 54
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Exploiting data parallelism in signal processing on a data flow machineNitezki, P. et al. | 1989
- 64
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Architectural mechanisms to support sparse vector processingIbbett, R.N. / Hopkins, T.M. / McKinnon, K.I.M. et al. | 1989
- 72
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A dynamic storage scheme for conflict-free vector accessHarper, D.T. III / Linebarger, D.A. et al. | 1989
- 78
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SIMP (single instruction stream/multiple instruction pipelining): a novel high-speed single processor architectureMurakami, K. / Irie, N. / Kuga, M. / Tomita, S. et al. | 1989
- 88
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2-D SIMD algorithms in the perfect shuffle networksBen-Asher, Y. / Egozi, D. / Schuster, A. et al. | 1989
- 96
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Systematic hardware adaptation of systolic algorithmsValero-Garcia, M. / Navarro, J.J. / Llaberia, J.M. / Valero, M. et al. | 1989
- 105
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Task migration in hypercube multiprocessorsChen, M.S. / Shin, K.G. et al. | 1989
- 114
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Characteristics of performance-optimal multi-level cache hierarchiesPrzybylski, S. / Horowitz, M. / Hennessy, J. et al. | 1989
- 122
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Supporting reference and dirty bits in SPUR's virtual address cacheWood, D.A. / Katz, R.H. et al. | 1989
- 131
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Inexpensive implementations of set-associativityKessler, R.E. / Jooss, R. / Lebeck, A. / Hill, M.D. et al. | 1989
- 140
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Organization and performance of a two-level virtual-real cache hierarchyWang, W.H. / Baer, J.L. / Levy, H.M. et al. | 1989
- 150
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High performance communications in processor networksJesshope, C.R. / Miller, P.R. / Yantchev, J.T. et al. | 1989
- 158
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Introducing memory into the switch elements of multiprocessor interconnection networksMizrahi, H.E. / Baer, J.L. / Lazowska, E.D. / Zahorjan, J. et al. | 1989
- 167
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Using feedback to control tree saturation in multistage interconnection networksScott, S.L. / Sohi, G.S. et al. | 1989
- 177
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Constructing replicated systems using processors with point to point communication linksEzhilchelvan, P.D. / Shrivastava, S.K. / Tully, A. et al. | 1989
- 186
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KCM: a knowledge crunching machineBenker, H. / Beacco, J.M. / Bescos, S. / Dorochevsky, M. / Jeffre, T. / Pohlmann, A. / Noye, J. / Poterie, B. / Sexton, A. / Syre, J.C. et al. | 1989
- 195
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A high performance Prolog processor with multiple function unitsSinghal, A. / Patt, Y.N. et al. | 1989
- 203
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Evaluation of memory system for integrated Prolog processor IPPMorioka, M. / Yamaguchi, S. / Bandoh, T. et al. | 1989
- 211
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A type driven hardware engine for Prolog clause retrieval over a large knowledge baseWong, K.F. / Williams, M.H. et al. | 1989
- 224
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Comparing software and hardware schemes for reducing the cost of branchesHwu, W.M.W. / Conte, T.M. / Chang, P.P. et al. | 1989
- 234
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Improving performance of small on-chip instruction cachesFarrens, M.K. / Pleszkun, A.R. et al. | 1989
- 242
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Achieving high instruction cache performance with an optimizing compilerHwu, W.W. / Chang, P.P. et al. | 1989
- 252
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The impact of code density on instruction cache performanceSteenkiste, P. et al. | 1989
- 262
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Can dataflow subsume von Neumann computing?Nikhil, R.S. / Arvind et al. | 1989
- 273
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Exploring the benefits of multiple hardware contexts in a multiprocessor architecture: preliminary resultsWeber, W.D. / Gupta, A. et al. | 1989
- 281
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Architectural and organizational tradeoffs in the design of the MultiTitan CPUJouppi, N.P. et al. | 1989
- 290
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Run-time checking in Lisp by integrating memory addressing and range checkingSato, M. / Ichikawa, S. / Goto, E. et al. | 1989
- 300
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Multiple vs. wide shared bus multiprocessorsHopper, A. / Jones, A. / Lioupis, D. et al. | 1989
- 307
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Performance measurements on a commercial multiprocessor running parallel codeAnnaratone, M. / Ruhl, R. et al. | 1989
- 315
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Interprocessor communication speed and performance in distributed-memory parallel processorsAnnaratone, M. / Pommerell, C. / Ruhl, R. et al. | 1989
- 325
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Analysis of computation-communication issues in dynamic dataflow architecturesGhosal, D. / Tripathi, S.K. / Bhuyan, L.N. / Jiang, H. et al. | 1989
- 336
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Logic simulation on massively parallel architecturesKravitz, S.A. / Bryant, R.E. / Rutenbar, R.A. et al. | 1989
- 344
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R256: a research parallel processor for scientific computationFukazawa, T. / Kimura, T. / Tomizawa, M. / Takeda, K. / Itoh, Y. et al. | 1989
- 354
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A three-port/three-access register file for concurrent processing and I/O communication in a RISC-like graphics engineAnido, M.L. / Allerton, D.J. / Zaluska, E.J. et al. | 1989
- 362
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An architecture framework for application-specific and scalable architecturesMulder, J.M. / Portier, R.J. / Srivastava, A. / Velt, R. in 't et al. | 1989
- 372
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Perfect Latin squares and parallel array accessKim, K. / Kumar, V.K.P. et al. | 1989
- 380
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An aperiodic storage scheme to reduce memory conflicts in vector processorsWeiss, S. et al. | 1989
- 387
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Analysis of vector access performance on skewed interleaved memoryChuen-Liang Chen / Chung-Kai Liao et al. | 1989
- 396
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Adaptive backoff synchronization techniquesAgarwal, A. / Cherian, M. et al. | 1989
- 407
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A cache consistency protocol for multiprocessors with multistage networksStenstrom, P. et al. | 1989
- 416
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On data synchronization for multiprocessorsSu, H.M. / Yew, P.C. et al. | 1989