Hardware Architecture for High-Performance Regular Expression Matching (English)
- New search for: Tsern-Huei, L.
- New search for: Tsern-Huei, L.
In:
IEEE TRANSACTIONS ON COMPUTERS
;
58
, 7
;
984-993
;
2009
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ISSN:
- Article (Journal) / Print
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Title:Hardware Architecture for High-Performance Regular Expression Matching
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Contributors:Tsern-Huei, L. ( author )
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Published in:IEEE TRANSACTIONS ON COMPUTERS ; 58, 7 ; 984-993
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Publisher:
- New search for: IEEE INSTITUTE OF ELECTRICAL AND ELECTRONICS
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Publication date:2009-01-01
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Size:10 pages
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ISSN:
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
- New search for: 621.38195 / 621.3
- Further information on Dewey Decimal Classification
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Classification:
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Source:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Table of contents – Volume 58, Issue 7
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 865
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Process-Variation-Aware Adaptive Cache Architecture and ManagementMutyam, M. / Feng Wang, / Krishnan, R. / Narayanan, V. / Kandemir, M. / Yuan Xie, / Irwin, M.J. et al. | 2009
- 865
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Cache Memory - Process-Variation-Aware Adaptive Cache Architecture and ManagementMutyam, M. et al. | 2009
- 878
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Efficient Software-Based Encoding and Decoding of BCH CodesJunho Cho, / Wonyong Sung, et al. | 2009
- 878
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Coding Theory - Efficient Software-Based Encoding and Decoding of BCH CodesCho, J. et al. | 2009
- 890
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A Floating-Point Unit for 4D Vector Inner Product with Reduced LatencyDonghyun Kim, / Lee-Sup Kim, et al. | 2009
- 890
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Computer Arithmetic - A Floating-Point Unit for 4D Vector Inner Product with Reduced LatencyKim, D. et al. | 2009
- 902
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Decimal Floating-Point MultiplicationErle, M.A. / Hickmann, B.J. / Schulte, M.J. et al. | 2009
- 917
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High-Performance Hardware Architectures for Galois Counter ModeSatoh, A. / Sugawara, T. / Aoki, T. et al. | 2009
- 931
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A Process Algebraic View of Latency-Insensitive SystemsKapoor, H.K. et al. | 2009
- 945
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A Homogeneous Architecture for Power Policy Integration in Operating SystemsPettis, N. / Yung-Hsiang Lu, et al. | 2009
- 931
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Formal Methods and Specifications - A Process Algebraic View of Latency-Insensitive SystemsKapoor, H.K. et al. | 2009
- 956
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Frame-Based Packet-Mode Scheduling for Input-Queued SwitchesJianyu Lou, / Xiaojun Shen, et al. | 2009
- 945
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Operating Systems, Software Systems, and Communication Protocols - A Homogeneous Architecture for Power Policy Integration in Operating SystemsPettis, N. et al. | 2009
- 956
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Scheduling - Frame-Based Packet-Mode Scheduling for Input-Queued SwitchesLou, J. et al. | 2009
- 970
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Collusive Piracy Prevention in P2P Content Delivery NetworksXiaosong Lou, / Kai Hwang, et al. | 2009
- 970
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Security - Collusive Piracy Prevention in P2P Content Delivery NetworksLou, X. et al. | 2009
- 984
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Hardware Architecture for High-Performance Regular Expression MatchingTsern-Huei Lee, et al. | 2009
- 984
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Theory and Algorithms - Hardware Architecture for High-Performance Regular Expression MatchingLee, T.-H. et al. | 2009
- 994
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Accurate Floating-Point Product and ExponentiationGraillat, S. et al. | 2009
- 994
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BRIEF CONTRIBUTIONS - Accurate Floating-Point Product and ExponentiationGraillat, S. et al. | 2009
- 1001
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Efficient Bit-Parallel GF(2^m) Multiplier for a Large Class of Irreducible PentanomialsCilardo, A. et al. | 2009
- c1
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[Front cover]| 2009
- c2
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[Inside front cover]| 2009
- c3
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TC Information for authors| 2009
- c4
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[Back cover]| 2009