Special Features - Optimizing Multiple EDA Tools within the ASIC Design Flow (English)
- New search for: Bening, Lionel
- New search for: Bening, Lionel
- New search for: Foster, Harry
In:
IEEE design & test of computers
;
18
, 4
; 46-55
;
2001
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ISSN:
- Article (Journal) / Print
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Title:Special Features - Optimizing Multiple EDA Tools within the ASIC Design Flow
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Contributors:Bening, Lionel ( author ) / Foster, Harry
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Published in:IEEE design & test of computers ; 18, 4 ; 46-55
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Publisher:
- New search for: Soc.
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Place of publication:Los Alamitos, Calif.
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Publication date:2001
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ISSN:
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ZDBID:
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
- New search for: 54.33 / 54.00
- Further information on Basic classification
- New search for: 770/3155
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Keywords:
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Classification:
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Source:
Table of contents – Volume 18, Issue 4
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 2
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Departments - EIC Message| 2001
- 4
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Features - Guest Editor's Introduction: Formal Verification of Commercial Integrated CircuitsPixley, Carl et al. | 2001
- 4
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Formal verification of commercial integrated circuitsPixley, C. et al. | 2001
- 6
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Features - Applied Boolean Equivalence Verification and RTL Static Sign-OffFoster, Harry et al. | 2001
- 6
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Applied Boolean equivalence verification and RTL static sign-offFoster, H. et al. | 2001
- 16
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Practical formal verification in microprocessor designJones, R.B. / O'Leary, J.W. / Seger, C.-J.H. / Aagaard, M.D. / Melham, T.F. et al. | 2001
- 16
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Features - Practical Formal Verification in Microprocessor DesignJones, Robert B. et al. | 2001
- 26
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Features - Design and Development Paradigm for Industrial Formal verification CAD ToolsKrishnamurthy, Narayanan et al. | 2001
- 26
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Design and development paradigm for industrial formal verification CAD toolsKrishnamurthy, N. / Abadir, M.S. / Martin, A.K. / Abraham, J.A. et al. | 2001
- 36
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Features - Coverage Metrics for Functional Validation of Hardware DesignsTasiran, Serdar et al. | 2001
- 36
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Coverage metrics for functional validation of hardware designsTasiran, S. / Keutzer, K. et al. | 2001
- 46
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Special Features - Optimizing Multiple EDA Tools within the ASIC Design FlowBening, Lionel et al. | 2001
- 46
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Optimizing multiple EDA tools within the ASIC design flowBening, L. / Foster, H. et al. | 2001
- 56
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A two-input, one-output bit-scalable architecture for fuzzy processorsD'Amore, R. / Saotome, O. / Kienitz, K.H. et al. | 2001
- 56
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Special Features - A Two-Input, One-Output Bit-Scalable Architecture for Fuzzy Processorsd'Amore, Roberto et al. | 2001
- 65
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Departments - Roundtable| 2001
- 72
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Departments - Conference Reports| 2001
- 73
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Departments - Panel Summaries| 2001
- 77
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Departments - DATC Newsletter| 2001
- 78
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Departments - TTTC Newsletter| 2001
- 80
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Departments - The Last Byte| 2001