The performance impact of block sizes and fetch strategies (English)
- New search for: Przybylski, S.
- New search for: Przybylski, S.
In:
Proceedings. The 17th Annual International Symposium on Computer Architecture
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160-169
;
1990
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ISBN:
- Conference paper / Print
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Title:The performance impact of block sizes and fetch strategies
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Additional title:Die Leistungsauswirkungen von Blockgrößen und Zugriffsstrategien
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Contributors:Przybylski, S. ( author )
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Published in:
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Publisher:
- New search for: IEEE Comput. Soc. Press
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Place of publication:Los Alamitos
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Publication date:1990
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Size:10 Seiten, 21 Quellen
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ISBN:
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DOI:
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Type of media:Conference paper
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Type of material:Print
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Language:English
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Keywords:
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 0_1
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Proceedings. The 17th Annual International Symposium on Computer Architecture (Cat. No.90CH2887-8)| 1990
- 2
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Weak ordering-a new definitionAdve, S.V. / Hill, M.D. et al. | 1990
- 15
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Memory consistency and event ordering in scalable shared-memory multiprocessorsGharachorloo, K. / Lenoski, D. / Laudon, J. / Gibbons, P. / Gupta, A. / Hennessy, J. et al. | 1990
- 27
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Synchronization with multiprocessor cachesLee, J. / Ramachandran, U. et al. | 1990
- 40
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Dynamic processor allocation in hypercube computersChuang, P.J. / Tzeng, N.F. et al. | 1990
- 50
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A new approach to fast control of r2*r2 3-stage Benes networks of r*r crossbar switchesYoussef, A. / Arden, B. et al. | 1990
- 60
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Virtual-channel flow controlDally, W.J. et al. | 1990
- 70
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Supporting systolic and memory communication in iWarpBorkar, S. / Cohn, R. / Cox, G. / Gross, T. / Kung, H.T. / Lam, M. / Levine, M. / Moore, B. / Moore, W. / Peterson, C. et al. | 1990
- 82
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Monsoon: an explicit token-store architecturePapadopoulos, G.M. / Culler, D.E. et al. | 1990
- 92
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The K2 parallel processor: architecture and hardware implementationAnnaratone, M. / Fillo, M. / Nakabayashi, K. / Viredaz, M. et al. | 1990
- 104
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APRIL: a processor architecture for multiprocessingAgarwal, A. / Lim, B.H. / Kranz, D. / Kubiatowicz, J. et al. | 1990
- 115
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PLUS: a distributed shared-memory systemBisiani, R. / Ravishankar, M. et al. | 1990
- 125
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Adaptive software cache management for distributed shared memory architecturesBennett, J.K. / Carter, J.B. / Zwaenepoel, W. et al. | 1990
- 138
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An empirical evaluation of two memory-efficient directory methodsO'Krafka, B.W. / Newton, A.R. et al. | 1990
- 148
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The directory-based cache coherence protocol for the DASH multiprocessorLenoski, D. / Laudon, J. / Gharachorloo, K. / Gupta, A. / Hennessy, J. et al. | 1990
- 160
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The performance impact of block sizes and fetch strategiesPrzybylski, S. et al. | 1990
- 172
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Performance comparison of load/store and symmetric instruction set architecturesAlpert, D. / Averbuch, A. / Danieli, O. et al. | 1990
- 182
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Reducing the cost of branches by using registersDavidson, J.W. / Whalley, D.B. et al. | 1990
- 192
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An investigation of static versus dynamic schedulingLove, C.E. / Jordan, H.F. et al. | 1990
- 204
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VAX vector architectureBhandarkar, D. / Brunner, R. et al. | 1990
- 216
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Multiple instruction issue in the NonStop Cyclone processorHorst, R.W. / Harris, R.L. / Jardine, R.L. et al. | 1990
- 228
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Performance of an OLTP application on Symmetry multiprocessor systemThakkar, S.S. / Sweiger, M. et al. | 1990
- 239
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The impact of synchronization and granularity on parallel systemsChen, D.K. / Su, H.M. / Yew, P.C. et al. | 1990
- 250
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Trace-driven simulations for a two-level cache design of open bus systemsBugge, H.O. / Kristiansen, E.H. / Bakka, B.O. et al. | 1990
- 260
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Performance measurement and trace driven simulation of parallel CAD and numeric applications on a hypercube multicomputerHsu, J.M. / Banerjee, P. et al. | 1990
- 270
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Generation and analysis of very long address tracesBorg, A. / Kessler, R.E. / Wall, D.W. et al. | 1990
- 282
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Fast Prolog with an extended general purpose architectureHolmer, B.K. / Sano, B. / Carlton, M. / Van Roy, P. / Haygood, R. / Bush, W.R. / Despain, A.M. / Pendleton, J.M. / Dobry, T. et al. | 1990
- 292
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Architectural support for the management of tightly-coupled fine-grain goals in Flat Concurrent PrologAlkalaj, L. / Lang, T. / Ercegovac Milos et al. | 1990
- 302
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Balance in architectural designHo, S. / Snyder, L. et al. | 1990
- 312
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A study of I/O behavior of Perfect benchmarks on a multiprocessorReddy, A.L.N. / Banerjee, P. et al. | 1990
- 322
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Maximizing performance in a striped disk arrayChen, P.M. / Patterson, D.A. et al. | 1990
- 332
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A distributed I/O architecture for HARTSShin, K.G. / Dykema, G. et al. | 1990
- 344
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Boosting beyond static scheduling in a superscalar processorSmith, M.D. / Lam, M.S. / Horowitz, M.A. et al. | 1990
- 355
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The TLB slice-a low-cost high-speed address translation mechanismTaylor, G. / Davies, P. / Farmwald, M. et al. | 1990
- 364
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Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffersJouppi, N.P. et al. | 1990