Hierarchical ATPG for Analog Circuits and Systems (English)
- New search for: Soma, M.
- New search for: Huynh, S.
- New search for: Zhang, J.
- New search for: Kim, S.
- New search for: Devarayanadurg, G.
- New search for: Soma, M.
- New search for: Huynh, S.
- New search for: Zhang, J.
- New search for: Kim, S.
- New search for: Devarayanadurg, G.
In:
IEEE DESIGN AND TEST OF COMPUTERS
;
18
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72-81
;
2001
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ISSN:
- Article (Journal) / Print
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Title:Hierarchical ATPG for Analog Circuits and Systems
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Contributors:Soma, M. ( author ) / Huynh, S. ( author ) / Zhang, J. ( author ) / Kim, S. ( author ) / Devarayanadurg, G. ( author )
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Published in:IEEE DESIGN AND TEST OF COMPUTERS ; 18 ; 72-81
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Publisher:
- New search for: IEEE INSTITUTE OF ELECTRICAL AND ELECTRONICS
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Publication date:2001-01-01
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Size:10 pages
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ISSN:
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
- New search for: 621.395
- Further information on Dewey Decimal Classification
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Classification:
DDC: 621.395 -
Source:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Table of contents – Volume 18
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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Departments - EIC Message| 2001
- 1
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EIC Message| 2001
- 3
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Guest editors' introduction: the new world of large embedded memoriesRajsuman, R. / Catthoor, F. et al. | 2001
- 3
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Features - Guest Editors' Introduction: The New World of Large Embedded MemoriesRajsuman, Rochit et al. | 2001
- 4
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Features - Guest Editors' Introduction: Roadmaps and Visions for Design and TestJoyner Jr, William H. et al. | 2001
- 4
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Guest Editors' Introduction: Roadmaps and Visions for Design and TestJoyner, W. H. / Kahng, A. B. et al. | 2001
- 4
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Features - Guest Editor's Introduction: Formal Verification of Commercial Integrated CircuitsPixley, Carl et al. | 2001
- 4
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Formal verification of commercial integrated circuitsPixley, C. et al. | 2001
- 4
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Guest Editor's Introduction: Formal Verification of Commercial Integrated CircuitsPixley, C. et al. | 2001
- 4
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Roadmaps and visions for design and testJoyner, W.H. / Kahng, A.B. et al. | 2001
- 5
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Perspectives: Moving the market to embedded memoryShubat, A. et al. | 2001
- 5
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Perspectives| 2001
- 5
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Departments - News| 2001
- 5
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Departments - Perspectives| 2001
- 6
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Dynamic power management of electronic systemsMacii, E. et al. | 2001
- 6
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Features - Applied Boolean Equivalence Verification and RTL Static Sign-OffFoster, Harry et al. | 2001
- 6
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Features - Guest Editors' Introduction: Dynamic Power Management of Electronic SystemsMacii, Enrico et al. | 2001
- 6
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Applied Boolean equivalence verification and RTL static sign-offFoster, H. et al. | 2001
- 6
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The design and test cost problemMaly, W. et al. | 2001
- 7
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Features - Guest Editors' Introduction: Application-Specific System-on-a-Chip MultiprocessorsWolf, Wayne et al. | 2001
- 7
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Guest editors' introduction: application-specific system-ona-chip multiprocessorsWolf, W. / Jerraya, A.A. et al. | 2001
- 7
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Bright future for programmable processorsKeutzer, K. et al. | 2001
- 7
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Features - Embedded DRAM Development: Technology, Physical Design, and Application IssuesKeitel-Schulz, Doris et al. | 2001
- 7
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Embedded DRAM development: Technology, physical design, and application issuesKeitel-Schulz, D. / Wehn, N. et al. | 2001
- 8
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Defect-oriented diagnosis for very deep-submicron systemsLombardi, F. / Metra, C. et al. | 2001
- 8
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Guest Editors' Introduction: Defect-Oriented Diagnosis for Very Deep-Submicron SystemsLombardi, F. / Metra, C. et al. | 2001
- 8
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Colif: A design representation for application-specific multiprocessor SOCsCesario, W.O. / Nicolescu, G. / Gauthier, L. / Lyonnard, D. / Jerraya, A.A. et al. | 2001
- 8
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Features - Guest Editors' Introduction: Defect-Oriented Diagnosis for Very Deep-Submicron SystemsLombardi, Fabrizio et al. | 2001
- 8
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Features - Colif: A Design Representation for Application-Specific Multiprocessor SOCsCesário, Wander O. et al. | 2001
- 8
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Creating a 100-horsepower car without 100 horsesAgarwal, V.K. et al. | 2001
- 9
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Potential showstoppers in technology and EDA roadmapsBorel, J. et al. | 2001
- 10
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Comparing system level power management policiesYung-Hsiang Lu, / De Micheli, G. et al. | 2001
- 10
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Technology will drive EDA's futureCamposano, R. et al. | 2001
- 10
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Features - Using Atomic Force Microscopy for Deep-Submicron Failure AnalysisLo, Jien-Chung et al. | 2001
- 10
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Features - Comparing System-Level Power Management PoliciesLu, Yung-Hsiang et al. | 2001
- 10
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Using atomic force microscopy for deep submicron failure analysisLo, J.-C. / Armitage, W.D. / Johnson, C.S. et al. | 2001
- 12
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Power-driven challenges in nanometer designSylvester, D. / Kaul, H. et al. | 2001
- 12
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Features - Power-driven Challenges in Nanometer DesignSylvester, Dennis et al. | 2001
- 16
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Practical formal verification in microprocessor designJones, R.B. / O'Leary, J.W. / Seger, C.-J.H. / Aagaard, M.D. / Melham, T.F. et al. | 2001
- 16
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Design and test of large embedded memories: An overviewRajsuman, R. et al. | 2001
- 16
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Features - Practical Formal Verification in Microprocessor DesignJones, Robert B. et al. | 2001
- 16
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Features - Design and Test of Large Embedded Memories: An OverviewRajsuman, Rochit et al. | 2001
- 19
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Poirot: applications of a logic fault diagnosis toolVenkataraman, S. / Drummonds, S.B. et al. | 2001
- 19
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Features - Poirot: Applications of a Logic Fault Diagnosis ToolVenkataraman, Srikanth et al. | 2001
- 20
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Intra-task voltage scheduling for low-energy hard real-time applicationsDongkun Shin, / Jihong Kim, / Seongsoo Lee, et al. | 2001
- 20
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Features - Intra-Task Voltage Scheduling for Low-Energy, Hard Real-Time ApplicationsShin, Dongkun et al. | 2001
- 21
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Viper: A multiprocessor SOC for advanced set-top box and digital TV systemsDutta, S. / Jensen, R. / Rieckmann, A. et al. | 2001
- 21
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Features - Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV SystemsDutta, Santanu et al. | 2001
- 23
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Platform-based design and software design methodology for embedded systemsSangiovanni-Vincentelli, A. / Martin, G. et al. | 2001
- 23
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Features - Platform-Based Design and Software Design Methodology for Embedded SystemsSangiovanni-Vincentelli, Alberto et al. | 2001
- 26
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Design and development paradigm for industrial formal verification CAD toolsKrishnamurthy, N. / Abadir, M.S. / Martin, A.K. / Abraham, J.A. et al. | 2001
- 26
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Features - Design and Development Paradigm for Industrial Formal verification CAD ToolsKrishnamurthy, Narayanan et al. | 2001
- 28
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Features - Using Electrical Bitmap Results from Embedded Memory to Enhance YieldSegal, Julie et al. | 2001
- 28
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Using electrical bitmap results from embedded memory to enhance yieldSegal, J. / Jee, A. / Lepejian, D. / Chu, B. et al. | 2001
- 31
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Defect-oriented testing and defective-part-level predictionDworak, J. / Wicker, J.D. / Lee, S. / Grimaila, M.R. / Mercer, M.R. / Butler, K.M. / Stewart, B. / Wang, L.-C. et al. | 2001
- 31
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Software energy reduction techniques for variable-voltage processorsOkuma, T. / Yasuura, H. / Ishihara, T. et al. | 2001
- 31
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Features - Software Energy Reduction Techniques for Variable-Voltage ProcessorsOkuma, Takanori et al. | 2001
- 31
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Features - Defect-Oriented Testing and Defective-Part-Level PredictionDworak, Jennifer et al. | 2001
- 32
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Automating the design of SOCs using coresBergamaschi, R.A. / Bhattacharya, S. / Wagner, R. / Fellenz, C. / Muhlada, M. / White, F. / Daveau, J.-M. / Lee, W.R. et al. | 2001
- 32
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Features - Automating the Design of SOCs Using CoresBergamaschi, Reinaldo A. et al. | 2001
- 34
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A mixed-signal design roadmapBrederlow, R. / Weber, W. / Sauerer, J. / Donnay, S. / Wambacq, P. / Vertregt, M. et al. | 2001
- 34
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Features - A Mixed-Signal Design RoadmapBrederlow, Ralf et al. | 2001
- 36
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Coverage metrics for functional validation of hardware designsTasiran, S. / Keutzer, K. et al. | 2001
- 36
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Features - Coverage Metrics for Functional Validation of Hardware DesignsTasiran, Serdar et al. | 2001
- 40
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Random-access data storage components in customized architecturesNachtergaele, L. / Catthoor, F. / Kulkarni, C. et al. | 2001
- 40
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Features - Random-Access Data Storage Components in Customized ArchitecturesNachtergaele, Lode et al. | 2001
- 42
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Features - Power Management in the Amulet MicroprocessorFurber, Steve B. et al. | 2001
- 42
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Power management in the Amulet microprocessorsFurber, S.B. / Efthymiou, A. / Garside, J.D. / Lloyd, D.W. / Lewis, M.J.G. / Temple, S. et al. | 2001
- 42
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Fault detection and location using I/sub DD/ waveform analysisMuhammad, K. / Roy, K. et al. | 2001
- 42
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Fault Detection and Location Using I~D~D Waveform AnalysisMuhammad, K. / Roy, K. et al. | 2001
- 42
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Power Management in the Amulet MicroprocessorFurber, S. B. / Lloyd, D. W. / Efthymiou, A. / Lewis, M. J. G. / Garside, J. D. / Temple, S. et al. | 2001
- 42
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Features - Fault Detection and Location Using IDD Waveform AnalysisMuhammad, Khurram et al. | 2001
- 46
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Optimizing multiple EDA tools within the ASIC design flowBening, L. / Foster, H. et al. | 2001
- 46
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Energy-aware runtime scheduling for embedded-multiprocessor SOCsPeng Yang, / Chung Wong, / Marchal, P. / Catthoor, F. / Desmet, D. / Verkest, D. / Lauwereins, R. et al. | 2001
- 46
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Special Features - Optimizing Multiple EDA Tools within the ASIC Design FlowBening, Lionel et al. | 2001
- 46
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Features - Energy-Aware Runtime Scheduling for Embedded-Multiprocessor SOCsYang, Peng et al. | 2001
- 47
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Strategies for low-cost testKapur, R. / Chandramouli, R. / Williams, T.W. et al. | 2001
- 47
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Features - Strategies for Low-Cost TestKapur, Rohit et al. | 2001
- 50
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IC diagnosis using multiple supply pad I/sub DDQ/sPlusquellic, J. et al. | 2001
- 50
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IC Diagnosis Using Multiple Supply Pad I~D~D~QsPlusquellic, J. et al. | 2001
- 50
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Features - IC Diagnosis Using Multiple Supply Pad IDDQsPlusquellic, Jim et al. | 2001
- 53
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Battery-driven dynamic power managementBenini, L. / Castelli, G. / Macii, A. / Scarsi, R. et al. | 2001
- 53
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Features - Battery Driven Dynamic Power ManagementBenini, Luca et al. | 2001
- 56
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Features - Data Memory Organization and Optimizations in Application-Specific SystemsPanda, Preeti Ranjan et al. | 2001
- 56
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Data memory organization and optimizations in application-specific systemsRanjan Panda, P. / Dutt, N.D. / Nicolau, A. / Catthoor, F. / Vandecappelle, A. / Brockmeyer, E. / Kulkarni, C. / De Greef, E. et al. | 2001
- 56
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A two-input, one-output bit-scalable architecture for fuzzy processorsD'Amore, R. / Saotome, O. / Kienitz, K.H. et al. | 2001
- 56
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High-accuracy flush-and-scan software diagnosticStanley, K. et al. | 2001
- 56
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Special Feature - High-Accurracy Flush-and-Scan Software DiagnosticStanley, Kevin et al. | 2001
- 56
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High-Accurracy Flush-and-Scan Software DiagnosticStanley, K. et al. | 2001
- 56
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Special Features - A Two-Input, One-Output Bit-Scalable Architecture for Fuzzy Processorsd'Amore, Roberto et al. | 2001
- 59
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Special ITC Section - Guest Editors' Introduction: Test Trade-Offs Take Center Stage at ITCAmbler, Tony et al. | 2001
- 59
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Guest editors' introduction: test trade-offs take center stage at ITCAmbler, T. / Wheater, D. et al. | 2001
- 60
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Very low cost testers: Opportunities and challengesBedsole, J. / Raina, R. / Crouch, A. / Abadir, M.S. et al. | 2001
- 60
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Special ITC Section - Very Low Cost Testers: Opportunities and ChallengesBedsole, Jay et al. | 2001
- 62
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Dynamic power management in wireless sensor networksSinha, A. / Chandrakasan, A. et al. | 2001
- 62
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Features - Dynamic Power Management in Wireless Sensor NetworksSinha, Amit et al. | 2001
- 63
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Special Features - Modeling a Verification Test System for Mixed-Signal CircuitsSan Segundo Bello, David et al. | 2001
- 63
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Modeling a verification test system for mixed-signal circuitsBello, D.S.S. / Tangelder, R. / Kerkhoff, H. et al. | 2001
- 65
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Departments - Roundtable| 2001
- 70
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Code transformations for data transfer and storage exploration preprocessing in multimedia processorsCatthoor, F. / Danckaert, K. / Wuytack, S. / Dutt, N.D. et al. | 2001
- 70
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Special ITC Section - Economics of Built-in Self-TestUngar, Louis Y. et al. | 2001
- 70
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Economics of built-in self-testUngar, L.Y. / Ambler, T. et al. | 2001
- 70
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Features - Code Transformations for Data Transfer and Storage Exploration Preprocessing in Multimedia ProcessorsCatthoor, Francky et al. | 2001
- 72
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Hierarchical ATPG for analog circuits and systemsSoma, M. / Huynh, S. / Zhang, J. / Kim, S. / Devarayanadurg, G. et al. | 2001
- 72
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Departments - Conference Reports| 2001
- 72
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Special Features - Hierarchical ATPG for Analog Circuits and SystemsSoma, Mani et al. | 2001
- 73
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Departments - Panel Summaries| 2001
- 76
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Current-based testing for deep-submicron VLSIsSachdev, M. et al. | 2001
- 77
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Special Features - Current-Based Testing for Deep-Submicron VLSIsSachdev, Manoj et al. | 2001
- 77
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Departments - DATC Newsletter| 2001
- 78
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Departments - TTTC Newsletter| 2001
- 80
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Special ITC Section - Test Resource Partitioning for SOCsChandra, Anshuman et al. | 2001
- 80
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Debugging using resublimated thiotimolineDavidson, S. et al. | 2001
- 80
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Departments - The Last Byte| 2001
- 80
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Test resource partitioning for SOCsChandra, A. / Chakrabarty, K. et al. | 2001
- 82
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Are single-chip multiprocessors in reach?Bergamaschi, R. / Bolsens, I. / Gupta, R. / Harr, R. / Jerraya, A. / Keutzer, K. / Olukotun, K. / Vissers, K. et al. | 2001
- 82
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Special Features - AD&T Roundtable: Are Single-Chip Multi-processors in Reach?| 2001
- 83
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System-on-chip testability using LSSD scan structuresZarrineh, K. / Upadhyaya, S.J. / Chickermane, V. et al. | 2001
- 83
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Special Features - System-on-Chip Testability Using LSSD Scan StructuresZarrineh, Kamran et al. | 2001
- 92
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Special ITC Section - Online and Offline BIST in IP-Core DesignBenso, Alfredo et al. | 2001
- 92
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Online and offline BIST in IP-core designBenso, A. / Chinsano, S. / Di Natale, G. / Prinetto, P. / Bodoni, M.L. et al. | 2001
- 95
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Departments - Standards| 2001
- 98
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Special Features - A D&T Roundtable: Industrial and University Test Research Collaboration| 2001
- 98
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Special Features - A Survey of Digital Design ReuseJacome, Margarida F. et al. | 2001
- 98
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A survey of digital design reuseJacome, M.F. / Peixoto, H.P. et al. | 2001
- 98
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Industrial and university test research collaborationAitken, R. / Cheng, T. / Nigh, P. / Stewart, B. / Roy, K. / Tollefson, G. et al. | 2001
- 100
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Special Feature - Making Java Work for Microcontroller ApplicationsIto, Sérgio Akira et al. | 2001
- 100
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Making Java work for microcontroller applicationsIto, S.A. / Carro, L. / Jacobi, R.P. et al. | 2001
- 108
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Automatic generation of parallel CRC circuitsSprachmann, M. et al. | 2001
- 108
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Special Features - Automatic Generation of Parallel CRC CircuitsSprachmann, Michael et al. | 2001
- 112
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Design closure with cell-based synthesisCarpenter, C. / McLellan, P. / Murgai, R. / Nikolic, B.B. / Sohail, F. / Sapatnekar, S. / Roy, K. et al. | 2001
- 115
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System-on-chip specification and modeling using C++: challenges and opportunities| 2001
- 115
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Roundtable| 2001
- 120
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Technology continuous educationSegura, J. et al. | 2001
- 122
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VHDL standardsAshenden, P.J. et al. | 2001
- 124
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Conference Reports| 2001
- 124
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Departments - New Products| 2001
- 127
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DATC Newsletter| 2001
- 128
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The last byte - two enduring questions for computer designJerraya, A. et al. | 2001
- 128
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The Last Byte| 2001
- 128
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The last byte - Test strategies and marriage partnersAmbler, T. et al. | 2001